1. Field of the Invention
The present invention relates to squelch detecting circuits, and particularly to a squelch detecting circuit used in a serial interface.
2. Description of the Background Art
Recently, interfaces used to send/receive digital data are in progress toward higher speed, smaller amplitude, more differentiation, and more serialization. Factors causing these trends include the need to process larger amounts of digital data. Sending/receiving larger amounts of digital data (e.g. images or motion pictures) without delay requires higher-speed interfaces. Increased speed can be achieved by raising the transfer clock speed, but it has physical limitations. Another way to achieve increased speed is to reduce amplitudes of sent/received signals. Reducing signal amplitudes increases through rates at rises and falls of signals and thus speeds up signal sending/receiving.
However, reducing signal amplitudes reduces noise tolerance. To avoid this problem, signals are differentiated to increase the noise tolerance. Also, serializing interfaces offers cross-talk resistance and enables lower-cost production. From these viewpoints, recent personal computers, peripheral devices, etc. adopt the USB2.0, for example. Also, SerialATA standard is now in progress to provide interfaces faster than USB2.0.
Such serial interfaces are provided with squelch detecting circuits for detecting whether signals contain data or not. Such squelch detecting circuits are often used to generate a kind of pattern according to data presence/absence time intervals and establish a pre-communication prior to data transmission and reception. Also, the squelch detecting circuits are circuits for detecting signal squelch (no-signal) condition. The squelch condition is defined as a condition in which input differential signals Vin+ and Vin− are at the same potential. However, in reality, it is difficult to cause the input differential signals Vin+ and Vin− to be perfectly at the same potential, but potential differences occur to some degree. For example, the SerialATA standard provides that a reference value for distinguishing squelch and non-squelch should be set between 50 mV and 200 mV in terms of the amplitude after converted to single-end. When the reference value is set at 100 mV, a signal amplitude of 50 mV after the single-end conversion is judged to be a squelch state and a signal amplitude of 150 mV after the single-end conversion is judged to be a non-squelch state (signal level).
Next, a conventional squelch detecting circuit is described. First, the squelch detecting circuit includes an operational amplifier that receives input differential signals and an operational amplifier that receives a voltage based on a squelch state judging reference. The plus outputs of these operational amplifiers are connected to each other and their minus outputs are connected to each other, too. Therefore the output differential signal exhibits a waveform in which an offset value is added on one side. When the individual operational amplifiers have a gain of one, the offset value is a voltage value based on the squelch state judging reference.
The differential signal with the offset value added on one side is amplified through plural stages of operational amplifiers to obtain a final signal. The differential signal with offset value added on one side includes a plus-side signal and a minus-side signal. When the plus-side signal and the minus-side signal have an amplitude larger than the offset value, then the signals are superimposed on each other to finally provide an output signal corresponding to the data. When the plus-side signal and the minus-side signal have an amplitude smaller than the offset value, then the signals are not superimposed and finally provide an output signal fixed at a low level. The conventional squelch detecting circuit thus operates to detect a squelch state and a non-squelch state.
The operation of the squelch detecting circuit is similar to that of a signal receiver circuit. However, the squelch detecting circuit which adds an offset value to detect a squelch state and a non-squelch state differs from the receiver circuit that requires no offset value. If a squelch detecting circuit is provided with a function as a receiver circuit, then the addition of the offset value affects the duty ratio of the finally obtained data. Therefore a receiver circuit is provided separately from the squelch detecting circuit.
Next, Japanese Patent Application Laid-Open Nos. 2002-344540 (pp. 8–19, FIGS. 1–14: this reference is hereinafter referred to as First Patent Document) and 2002-344541 (pp. 7–16, FIGS. 1–10: this reference is hereinafter referred to as Second Patent Document) describe improvements of conventional squelch detecting circuits. In the squelch detecting circuits described in First and Second Patent Documents, a peak hold circuit holds a peak value of an input signal at a given node. Then, while the potential at the given node varies as the peak hold circuit holds the peak value, a constant-potential setting circuit constantly brings it back to a given potential with a time constant larger than the potential variation caused by the holding of the peak value. Then a comparator circuit compares with a given reference level the potential at the node that is held at the peak value and slowly brought back to the given potential and outputs the result of the comparison as a detect signal.
However, in order to obtain a final output signal from input differential signals, conventional squelch detecting circuits are required to provide amplifying performance equivalent to or higher than that of receiver circuits. Therefore conventional squelch detecting circuits require plural stages of operational amplifiers and consume huge power. In fact, the USB2.0 (with a transfer rate of 480 Mbps) requires six to seven stages of operational amplifiers. Also, high transfer rates, like that of USB2.0, require operational amplifiers to operate at high speed, leading to increased cost of parts.
Moreover, when a plurality of operational amplifiers are provided, the amplification factors of individual operational amplifiers vary due to electrical characteristic differences among them, temperature variations during operation, and supplied voltage variations. The variations of individual operational amplifiers make it difficult for the conventional squelch detecting circuits to operate steadily.
The squelch detecting circuits described in First and Second Patent Documents cited above use peak hold circuits and therefore, unlike other conventional squelch detecting circuits, they do not need plural stages of operational amplifiers. Thus the squelch detecting circuits described in First and Second Patent Documents can solve the above-described problems. However, since the circuit configurations of the squelch detecting circuits described in First and Second Patent Documents include feedback portions, the held peak values are limited. A squelch detecting circuit with limited peak value can operate up to the transfer rate of 480 Mbps of USB2.0, but, with SerialATA with a transfer rate of 1.5 Gbps, such a squelch detecting circuit with limited peak value may be unable to obtain sufficient gain and unable to operate.